Hw-breakpoint: found 6 breakpoint and 1 watchpoint registers. Print_constraints: vdd3p0: 2800 3150 mV at 3000 mV fast normal Print_constraints: vdd1p1: 800 1400 mV at 1100 mV fast normal Print_constraints: vdd2p5: 2000 2775 mV at 2400 mV fast normal Print_constraints: vddsoc: 725 1300 mV at 1200 mV fast normal Print_constraints: vddcore: 725 1300 mV at 1150 mV fast normal Print_constraints: vddpu: 725 1300 mV at 1150 mV fast normal SMP: Total of 4 processors activated (6324.22 BogoMIPS).
Hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available MXC_Early serial console at MMIO 0x2020000 (options '115200')Ĭalibrating delay loop. Sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms Preemptible hierarchical RCU implementation. Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) PID hash table entries: 2048 (order: 1, 8192 bytes)ĭentry cache hash table entries: 65536 (order: 6, 262144 bytes) Kernel command line: console=ttymxc0,115200 nsole=ttymxc0 vmalloc=400M init=/init video=mxcfb1:off video=mxcfb2:off fbmem=28M
PERCPU: Embedded 7 pages/cpu s5760 r8192 d14720 u32768īuilt 1 zonelists in Zone order, mobility grouping on. Memory policy: ECC disabled, Data cache writeallocĬPU identified as i.MX6Q, silicon rev 1.2 Machine: Freescale i.MX 6Quad/DualLite/Solo Sabre-SD Board Linux version 3.0.35-05236-gc9dfae3 (gcc version 4.4.3 (GCC) ) #3 SMP PREEMPT Mon May 6 17:06:ĬPU: ARMv7 Processor revision 10 (ARMv7), cr=10c53c7dĬPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Net: got MAC address from IIM: 00:00:00:00:00:00įastboot is in init.flash target is MMC:3īad partition index:2 for partition:recoveryīad partition index:5 for partition:system *** Warning - bad CRC or MMC, using default environment MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3 Temperature: 34 C, calibration data 0x5774e769īoard: i.MX6Q-SABRESD: unknown-board Board: 0圆3012
CPU: Freescale i.MX6 family TO1.2 at 792 MHz
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